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Browse materialsMIT 6.374 · Fall 2003

Analysis and Design of Digital Integrated Circuits

Subject: Engineering

Art: not stated, Fletcher's Combined Block Telegraph Apparatus and Bell, 1889 · Public domain

Instructor: Prof. Anantha Chandrakasan
Term: Fall 2003
Level: Graduate
What's inside: 1 lecture note · 1 reading · 23 other files · 6 web pages
Materials open: MIT OCW

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About this course

Source: MIT OpenCourseWare 6.374 Analysis and Design of Digital Integrated Circuits, Fall 2003, Prof. Anantha Chandrakasan — original course page on ocw.mit.edu ↗. License: CC BY-NC-SA 4.0. Study order: MIT's own listing order, section by section. Taken from MIT's published course files, downloaded from ocw.mit.edu on September 23, 2026. How RedLectern is built.

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Prerequisites are not listed here. Check MIT's own syllabus for this course.

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15 files

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Exams

MIT OpenCourseWare, Prof. Anantha Chandrakasan, 6.374 Analysis and Design of Digital Integrated Circuits, Fall 2003.

License: CC BY-NC-SA 4.0 · Edition: Fall 2003 · Open the original course on OCW ↗

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Analysis and Design of Digital Integrated Circuits

Before you start

What's here, and what isn't

Not included here

Materials by section

Assignments

Projects

Tools

Exams

Lecture 1: Challenges in Digital IC Design Course Overview

Lecture 2: CMOS Inverter I MOS Device Model with Sub-micron Effects VTC Parameters - DC Characteristics

Lecture 3: CMOS Inverter II CMOS Propagation Delay Parasitic Capacitance Estimation Layout of an Inverter Supply and Threshold Voltage Scaling SPICE Simulation Techniques

Lecture 4: CMOS Inverter III Components of Energy and Power Switching, Short-Circuit and Leakage Components SPICE Simulation Techniques

Lecture 5: Combinational Logic I Static CMOS Construction Ratioed Logic

Lecture 6: Combinational Logic II Pass Transistor / Transmission Gate Logic DCVSL Introduction to Dynamic Logic

Lecture 7: Combinational Logic III Dynamic Logic Design Considerations Power Dissipation in CMOS

Lecture 8: Combinational Logic IV Power Consumption in CMOS Logic (cont.) Leakage Power Dissipation Logical Effort Sizing - Performance Optimization of Digital Circuits

Lecture 9: Arithmetic Structures / Bit Slice Design Adders, Multipliers, Shifters Design Methodology Layout Techniques and Mapping Project Schedule and Guidelines

Lecture 10: Evening Session on Exploring Project Ideas Finish Arithmetic Structures and Project Ideas

Lecture 11: Guest Lecture by Prof. Tayo Akinwande Integrated CMOS Processing

Lecture 12: Sequential Circuits I Classification / Parameters Static Latches and Register

Lecture 13: Sequential Circuits II Race Condition Dynamic Latches and Registers Two Phase vs. Single Phase

Lecture 14: Sequential Circuits III Pulse Based Registers Latch vs. Register Systems Metastability

Lecture 15: Interconnect Capacitance Estimation Buffer Chains Low Swing Drivers Power Distribution

Lecture 16: Interconnect (cont.) Issues in Timing - Impact of Clock Skew and Jitter

Lecture 17: Clock Distribution Origins of Clock Skew / Jitter and Impact on Performance Clock Distribution Techniques Self-timed Circuits

Lecture 18: Memory I: ROM / EPROM / PLA Design Organization / Architecture Cell Design Sense-amplifiers PLA Folding Techniques Self-timing

Lecture 19: Memory II: SRAM Design Cell Design Differential Sense Amplifiers Self-timing

Lecture 20: Memory III DRAM Design Single Ended Sense Amplifier CMOS Scaling

Lecture 21: Advanced Voltage Scaling Techniques DC-DC Converter Design Performance Feedback Dynamic Voltage / Frequency Scaling

Lecture 22: Power Reduction Through Switching Activity Reduction Testing in VLSI Defects, Fault Models, Path Sensitization Scan, Built-in-self Test, IDDQ

Lecture 23: Presentation of Final Projects

Lecture 24: Presentation of Final Projects (cont.)